1. Field of the Invention
The present invention relates to an evaluation TEG (test element group) in an element having an SOI structure, which is capable of extracting a capacitance of a parasitic transistor in an edge region, which is produced by an LOCOS, and a method of estimating an effective film thickness and impurity density of the parasitic transistor without breakdown of the device.
2. Description of the Related Art
In a semiconductor device using a SOI (silicon on insulator) substrate, a parasitic transistor is formed in an edge between a silicon layer and a LOCOS (local oxidation of silicon) oxide film. A structure of the parasitic transistor is shown in FIG. 10(a).
In FIG. 10(a), a BOX layer 110, which is an oxide layer, an SOI layer 120, a gate oxide layer 130, and an electrode 140 are formed on a bulk layer 100 in this order. Each element is separated by a LOCOS 150 and a parasitic transistor is formed in a birdbeak (parasitic) portion P of the LOCOS 150 surrounded by a circle.
The parasitic transistor causes hump characteristics (increase of leakage current) in the basic characteristics of MOSFET (MOS field effect transistor) of the SOI. In order to evaluate the hump characteristics, a sectional SEM observation method, wherein a wafer is cut for monitor, and other method, wherein a process factor is estimated from the process dependency of the sub-threshold characteristics, are used. In FIG. 11, are shown the sub-threshold characteristic of gates formed by various processes.
The former method, the sectional SEM observation method using photographs, is to directly inspect a sectional structure. The latter method using the sub-threshold characteristic is to monitor the appearance of the hump by changing process conditions for causing the hump.
An example of the prior art using the evaluation TEG is disclosed in Japanese Patent Application Kokai Number 7-260867, although it does not correspond to the SOI structure. In the evaluation TEG, the area of the gate and the shapes of the gate and the LOCOS birdbeak portion can be handled as independent parameters. A transistor sample for evaluation use is formed with such an evaluation TEG for evaluating the reliability of the gate oxide film. Even an unrealistic gate oxide film can be easily formed and evaluated by the evaluation TEG. An accurate evaluation result can be obtained quickly by a simple operation.
However, there are problems in the prior art mentioned below.    (1) An expensive SOI wafer is broken down in the sectional SEM observation method.    (2) A wafer used for the sectional SEM observation method and an actual wafer subject to an electrical test are not always identical because a sample for the sectional SEM observation method requires a relatively large dimension, while a sample for the electrical test is small.    (3) In the latter method for evaluating the factor of the hump characteristics from the process dependency (the impurity density and oxide film thickness) of the sub-threshold characteristics, it is difficult to judge which is a real factor, the impurity density is small or the gate oxide film in the edge region is thick.
Also, a plurality of wafers are required for changing the process conditions.